发明名称 |
SEMICONDUCTOR MEMORY INTEGRATED CIRCUIT |
摘要 |
PURPOSE:To increase alpha-ray resistivity by making a conductive P-type layer of an impurity layer which consists of regions formed below or between circuit devices of a memory cell array and by making a depletion p-type layer of an impurity layer which consists of regions formed below or between circuit elements in a peripheral circuit. CONSTITUTION:A memory cell array consists of a number of circuit devices which are composed of an impurity layer partially formed within a semiconductor substrate 100 and a plurality of memories made of the circuit elements are arranged in matrix wherein. A peripheral circuit selects the memory cells and conducts read and write operation. Impurity layers having reverse polarity against an impurity layer constituting the circuit element and whose impurity densities are different each other are formed below or between circuit devices constituting a memory cell array and a peripheral circuit. In this way, alpha-ray resistivity of a memory cell to be microstructured can be improved without increasing parasitic capacity of the peripheral circuit. |
申请公布号 |
JPH01157567(A) |
申请公布日期 |
1989.06.20 |
申请号 |
JP19880234980 |
申请日期 |
1988.09.21 |
申请人 |
HITACHI LTD |
发明人 |
TANAKA HIRONORI;YAMASHITA HIROKI;MASUDA NOBORU;SHIGETA JUNJI;UMEMOTO YASUNARI;KAGAYA OSAMU |
分类号 |
H01L27/10;H01L27/095;H01L29/80 |
主分类号 |
H01L27/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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