发明名称 LOGICAL CIRCUIT
摘要 PURPOSE:To test and evaluate the whole logical circuit including flip-flops at a time by constituting the logical circuit so as to be operated by regarding each flip-flop as a kind of gate at the time of test and evaluation and inputting an input signal to the flip-flop in parallel to observe the output. CONSTITUTION:When a signal generating circuit 6 and a switching circuit 5 are connected to each of all the flip-flops constituting said logical circuit, it is unnecessary to fix the output of the flip-flop by actuating the flip-flop with a system clock at the time of test and evaluation. In addition, these flip-flops can be used as gates. If a switch S1 is turned on simply by a control signal Pc without changing the logical constitution of the circuit at the time of test and evaluation to input an input signal (a) to the flip-flop 4, the signal generating circuit 6 generates an operation clock signal C for the flip-flop 4 automatically on the basis of the input signal (a). Consequently, the relation between the input and output can be recognized clearly when the logical circuit is tested and evaluated.
申请公布号 JPS58213528(A) 申请公布日期 1983.12.12
申请号 JP19820096164 申请日期 1982.06.07
申请人 HITACHI SEISAKUSHO KK 发明人 IWASA SHINICHI
分类号 H03K3/037;H03K19/00 主分类号 H03K3/037
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