GEINTEGREERDE GEHEUGENSCHAKELING MET INTERNE VOEDINGSSPANNINGSREGELING.

摘要

The invention relates to an integrated memory circuit which acts on an internal supply voltage which is valued below an externally applied supply voltage. The bit lines and non-bit lines are charged to the internal supply voltage VDI whereto the memory cells are also connected. Before a read mode the bit line and the non-bit line selected by a column selection signal are discharged to a voltage value VDIT which is valued one threshold voltage of an NMOS transistor below the internal supply voltage. As a result, the maximum insusceptibility to noise is maintained for the memory cells and the data bit of high potential on one side of the memory cell can no longer be disturbed during the read cycle. The invention also relates to a circuit for generating the discharge voltage VDIT for the bit line and the non-bit line, which discharge voltage is valued one threshold voltage below the internal supply voltage VDI of the memory. This circuit comprises a charging branch for charging a capacitor to the voltage VDIT and a discharging branch for discharging this capacitor to the voltage VDIT in the situation where the voltage across the capacitor excessively rises beyond the voltage VDIT due to the repeated charge transfer from the bit line pairs to said capacitor.