| 摘要 |
<p>PURPOSE:To easily obtain a break generating circuit by using an address information output means which sends a fetch address and an execution address under execution to a bus line in time division and a means which sends said two addresses to the outside. CONSTITUTION:A bus interface control unit 3 serves also as an address output means and an address information output means of a microprocessor. In case an instruction executing cycle overlaps a fetch cycle as shown by fetch addresses FA1-FA4, these addresses are sent to an address bus with a first clock and then the executing addresses EA1, EA3, EA4, and EA6 are outputted with the next clock respectively. Then the executing addresses EA2 and EA5 are outputted as they are to an external address bus 25 in the cycles except the fetch cycles, i.e., in the single executing address cycles EA2 and EA5. It is shown by two types of address strobe signals whether a fetching or executing address is presently delivered.</p> |
