The invention relates to a digital data processor based upon the pipeline control system, which is particularly effective when the time required for reading a microprogram is relatively short. A microcycle is based upon the time required for reading the microprogram, and the operations on the data is executed in a pipeline system by dividing it up according to the determined microcycle. This is done by providing a destination latch register on the output side of the arithmetic unit. The invention further deals with the processors in which the destination latch register is provided on the input side of the arithmetic unit, or when the destination latch register is incorporated within the arithmetic unit, and a circuit setup for avoiding any contention for a register that may develop when executing a current instruction and the next instruction is provided in accordance with an added microprogram.
