| 摘要 |
PURPOSE:To realize a high speed operation of an element and realize a substantially fine unit cell size by a method wherein an arrangement structure which enables a contact hole to be omitted so as to reduce the resistance of a control gate electrode wiring significantly and to have the size of the unit cell determined by an element isolation capability and the spacing between floating gate electrodes. CONSTITUTION:Element isolation regions 22 are formed in a self-alignment manner with floating gate electrode patterns 32. Low resistance silicide layers 29 and source/ drain regions 27 are provided in parallel to the long side direction of the floating gate electrode patterns 32 and control gate electrode patterns 31 are provided in parallel to the short side direction of the floating gate electrode patterns 32. Therefore, the control gate electrode wiring length is reduced and the resistance of the control gate electrode wiring is significantly reduced so that a significantly high speed operation of an element can be realized. Further, as the low resistance silicide layers 29 and the source/drain layers 27 which are equivalent to bit lines are employed, a half contact hole for one cell can be omitted so that the unit cell whose size is as fine as the limit cell area determined by the minimum spacing between the floating gate electrode and the minimum area of the floating gate electrode can be realized. |
