BIT SYNCHRONIZING CIRCUIT

摘要

PURPOSE:To attain the switching of a frequency division ratio in a variable frequency divider circuit in a prescribed timing by inserting a monostable multivibrator between an edge differentiation circuit and an up-down counter of a bit synchronizing circuit. CONSTITUTION:The monostable multivibrator 13 is connected between an edge differentiation circuit 4 of a loop circuit 3 and an up-down counter circuit 8. Thus, two consecutive pulse reception clock signals due to noise of a base band signal are given to the monostable multivibrator 13 from the edge differentiation circuit 4 at each period of the base band signal, then the monostable multivibrator 13 outputs a pulse signal with a pulse width tau synchronously with the 1st reception clock signal and the pulse signal synchronously with the 2nd reception clock signal is not outputted. Thus, the switching of the frequency division ratio in the variable frequency division circuit 9 is applied in a prescribed timing.