发明名称 Synchronizer having dual feedback loops for avoiding intermediate voltage errors
摘要 A synchronizer is comprised of a voltage amplifier having an input terminal for receiving a voltage sample and an output terminal for generating an output voltage that is inversely proportional to the voltage of the input terminal. Also, a first feedback circuit couples the output terminal to a control transistor internal to the amplifier, and a second feedback circuit couples the output terminal to the input terminal. The first feedback circuit together with the control transistor has a fast response time, in comparison to the second feedback circuit; and it operates to quickly increase the output voltage when the voltage sample on the input terminal is below a predetermined level, and vice versa, without altering the voltage sample on the input terminal. And, the second feedback circuit operates to slowly modify the voltage sample on the input terminal in inverse proportion to the output terminal voltage.
申请公布号 US4839541(A) 申请公布日期 1989.06.13
申请号 US19880208464 申请日期 1988.06.20
申请人 UNISYS CORPORATION 发明人 GAL, LASZLO V.;ARRAUT, FERNANDO W.;KHOSRAVI, CHRISTOPHER H.
分类号 G06F15/16;G06F15/177;H03K3/356 主分类号 G06F15/16
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