| 摘要 |
PURPOSE:To obtain a synchronizing step-out detecting circuit by detecting the errors of n-bits or above among m-bits, in which frame synchronizing patterns are successive, in a receiving digital code string in which respective bits of the frame synchronizing patterns are arranged at the same interval. CONSTITUTION:An exclusive OR gate 2 compares a bit string added to a receiving digital code string input terminal 5 with the output of a frame synchronizing pattern generating part, and at the time of discrepancy, namely, the time of an error generation, the gate goes to 1. The output is composed of m-pieces of data FF31-33, and it is given to a m-bit length shift register 3 to execute a shifting action by the trailing edge of a pulse given to a synchronizing pattern pulse input terminal 7. Consequently, the register 3 records the error condition of the frame synchronizing bits of past m-bits. Since an n-bit 1 detecting part 4 outputs 1 when n-number or above of signals among (m) input signals are 1, the part is made into 1 when the errors of n-bits or above exist in the frame synchronizing bits of the past m-bits, and the synchronizing step-out can be detected. |
