| 摘要 |
In a processor array comprising first through N-th processors, each of first through (N-1)-th switching devices is connected between preceding and succeeding processors of two consecutively numbered ones of the first through the N-th processors. Each processor comprises at least one processor module between a processor input bus and a processor output bus. A controlling unit controls the first through the (N-1)-th switching devices so that the processor input and output buses of the first through the N-th processors are selectively connected together. Each processor may further comprise a feedback bus connected to the at least one module. In this case, the first through the (N-1)-th switching devices are controlled so that the feedback buses of the first through the N-th processors are selectively connected in series in compliance with the manner in which the processor input and output buses of the first through the N-th processors are connected together. When each processor comprises a plurality of processor modules, the controlling unit may furthermore control the processor modules of each processor so that the processor modules of each processor are selectively operable. The processor modules of one or more processors may process partial blocks of each principal block of a digital video signal, respectively, during a time duration of the principal block. The control unit may put the processor modules into operation either only once in each time duration or repeatedly in a time division fashion. |
