发明名称 NOISE ELIMINATING CIRCUIT
摘要 PURPOSE:To prevent malfunction of the device due to noise invaded in a reception signal by using an output of a frequency-division means frequency-dividing a reference clock to be inputted to generate clocks with different periods so as to sample the input signal invaded with noise and applying logic processing to reproduce the signal into a signal from which the noise is rejected. CONSTITUTION:With an input signal mixed with noise B at level 0 as shown in figure a-1 fed to a shift register(SR) 2, the signal is sampled by a clock CK-1 having a sufficiently smaller period than the period of the input signal in the shift register and fetched sequentially and shifted and outputted in parallel. Since the outputs are ORed by an OR gate 22, the noise of 0 level is rejected. On the other hand, with an input signal mixed with noise B' at level 1 as shown in figure b-1 given, an output shown in figures b-3, 5 is obtained from the SR 21 and a D-FF 23. The signal is sampled by a CK-3 shown in figure a-6 and fetched in an SR 24, shifted and fed to an AND gate 25. Since not all 3-inputs go to 1, the output goes to 0 and the noise of level 1 is eliminated.
申请公布号 JPH01146422(A) 申请公布日期 1989.06.08
申请号 JP19870305313 申请日期 1987.12.02
申请人 FUJITSU LTD 发明人 YUZAWA HIROSHI
分类号 H03K5/1252;H03K5/01;H04L25/08 主分类号 H03K5/1252
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