Arrangement and construction of output control circuit in semiconductor memory device.

摘要

In a semiconductor memory device of this invention, output control circuits (26A, 26B) are provided adjacent to column sense amplifiers (25A, 25B) and output transistors (Qp, Qn) are provided at a distance from the output control circuits (26A, 26B). The wiring length ( DELTA L1) of a wiring (36) from the column sense amplifiers (25A, 25B) to the output control circuits (26A, 26B) is set to be shorter than the wiring length ( DELTA L2) of a wiring (37) from the output control circuits (26A, 26B) to the output transistors (Qp, Qn).