| 摘要 |
A method and apparatus for resetting a SRAM in a single DRAM-SRAM transfer cycle in a graphics system is described comprising a SRAM address decoder, a DRAM data input buffer, a reset data register and data lines. In operation, reset data is transferred into the DRAM data input buffer. Thereafter, the SRAM is isolated from the address decoder and the data lines and the reset data is transferred from the DRAM data input buffer into the reset data register. Then data is transferred in parallel between the DRAM and the SRAM. Upon completion of the transfer of data between the DRAM and the SRAM, the SRAM is recoupled to the data lines. After the SRAM is recoupled to the data lines, the reset data is transferred in parallel to the SRAM. Upon the transfer of the reset data to the SRAM, the system is returned to its pre-transfer cycle condition.
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