| 摘要 |
PURPOSE:To obtain an accurate output clock pulse with less fluctuation in an output clock period data by interrupting the supply to an output clock generating circuit if the output clock period data is fluctuated and supplying the output clock period data stored before the fluctuation. CONSTITUTION:An output clock pulse CKOUT and an edge of an input signal SIN are compared by a phase error detection circuit 10. If the input signal SIN is interrupted, the output clock period data D0 outputted from an output clock period detection circuit 30 becomes a different data, a fluctuation detection section 41 of a period data fluctuation detecting circuit 40 controls a changeover means 41 to send the output clock period data D1 stored by a memory means 43 to the output clock generating circuit 20. The output clock period data D1 stored by the memory means 43 is data latched by the 1st latch circuit 44 when the output clock period data D0 are equal over 6 words. |
