| 摘要 |
PCT No. PCT/GB86/00675 Sec. 371 Date Aug. 31, 1987 Sec. 102(e) Date Aug. 31, 1987 PCT Filed Oct. 31, 1986 PCT Pub. No. WO87/02825 PCT Pub. Date May 7, 1987.A method (FIG. 3) for producing MOS transistors of the type having shallow, lightly doped, source/drain structure. In this method sidewall fillets (7) of n-type doped dielectric material are defined adjacent to the sides of the oxide (1) and metal electrode (3) features. These fillets (7) are then employed to provide self aligned masking during implantation of heavy dopant of either n- or p- type (9; 13). In a subsequent rapid anneal step, the implant dopant is activated and n-type dopant diffused into the substrate (5) from the fillets (7) to provide lightly doped source/drain structures (11; 15). Examples of this method are described for producing phosphorus-arsenic n-/n+ are phosphorus-boron p-/p+ source/drain structures.
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