| 摘要 |
PURPOSE:To reduce the IC chip size and the power consumption by devising the generator such that a synchronizing pulse is obtained even when a frequency of a clock input signal is halved. CONSTITUTION:When a leading edge of an input signal X arrives, an output of an inverted output terminal Q' of a FF 1 goes from '1' to '0', then the output of a coincident gate 11 goes from '0' to '1', and since the signal X is at H, the output of a coincident gate 12 goes from '1' to '0' each reset of FFs 2, 3 is released and an output signal F2 at a noninverting output Q of the FF 2 goes from '0' to '1' at a time t1 and a Q output signal F3 of a FF 3 goes from '0' to '1' at a time t2. As a result, 1s are arranged to the input of a coincidence gate 13, the output goes to '0' a reset pulse is outputted to restore the waveform F1 to '1'. Each waveform of F2, F3 is restored from '1' to '0' at times t3, t4 and a reset pulse is obtained during a half clock from the time t2 to t3. Moreover, an H signal is generated during a period of t1-t4 at the output of the coincident gate 14 to reset the FF 2, 3 after a time t4 thereby inhibiting the reception of each input. |
