| 摘要 |
<p>PURPOSE:To reduce the load capacity of a boosting circuit and to reduce semiconductor chip area by charging with high electric potential electric power supply in the early period during the charging period of a word line and charging the word link by a boosting electric power supply in the latter period. CONSTITUTION:On reading, an address signal inputted to address signal input terminals 1a-1c is made into a logic '1' first. Thus, the output of an inverter 4 becomes the logic '1'. In this case, since FET 25 is in ON state, a word line 14 is charged to a high electric potential electric power supply level by the inverter 4. On the other hand, since an address sign of which logical value is zero is inputted to address signal input terminals 2a-2c. FET 8-10 become an ON state. However, since FET 7 is an OFF state, the voltage of a boosting electric power supply terminal 13 is not applied to the line 14. Then, when the line 14 reaches the high electric potential electric power supply level, FET 7 becomes an ON state and FET 25 becomes OFF state. Consequently, the line 14 is charged by the boosting electric power supply level of the terminal 13. Thus, the load capacity of the boosting circuit is reduced and the capacitor capacity can be minimized.</p> |
