| 摘要 |
<p>PURPOSE:To reduce a required layout area by coupling memory cells arranged at addresses corresponding to plural memories having fundamental constitution of different kinds of memory cells with a common address selection line, and sharing an address decoder by the plural memories. CONSTITUTION:In an address conversion buffer included in the memory managing device of a digital processing system employing a virtual storage system, etc., the memory cells MC1 and MC2 arranged at the addresses corresponding to the plural memories RAM and FR having the fundamental constitution of the different kinds of memory cells MC1 and MC2 are coupled with the common address selection lines W0-Wm. Therefore, the address decoder AD can be shared by the plural memories RAM and FR. In such a way, it is possible to reduce the required layout area of the address conversion buffer, etc., including the plural memories RAM and FR.</p> |
