| 摘要 |
PURPOSE:To self-align a bipolar transistor with a CMOS transistor and to enhance an operating speed and integration density by forming a multilayer structure composed of a first insulating film, a first polycrystalline semiconductor film, a second insulating film and a second polycrystalline semiconductor film. CONSTITUTION:A structure on a main face of a semiconductor layer for a base-emitter region of a bipolar transistor 100 as well as for a source-drain region and a gate region of individual MOS transistors 201, 202 is constituted by a four-layer structure composed of a first insulating film 18, a first polycrystalline semiconductor film 10, a second insulating film 19 and a second polycrystalline semiconductor film 11. Accordingly, when an active region of each transistor is to be formed, a size to be finished can be controlled by using a side-etching technique for easy fine processing, and a self-alignment technique can be applied. An emitter width S of the bipolar transistor, an interval D between a base extraction electrode and an emitter diffusion layer and a gate length L of each MOS transistor can be shortened; it is possible to obtain a high-speed and high-integration semiconductor device of a Bi-CMOS LSI.
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