| 摘要 |
<p>PURPOSE:To prevent a malfunction by supplying a new basic clock and an updated (n)-fold clock in the same phase relation as a logical phase function between a basic clock and an (n)-fold clock stopped from being supplied in a clock switching in a clock synchronizing type system. CONSTITUTION:The presence and absence of an abnormality is detected by a selection instructing circuit 12 concerning clocks from plural clock distributing sources, the clock having no abnormality is selected by a selecting circuit 11. That a selection instruction signal is generated in what logical phase relation a pair of the basic clock and the (n)-fold clock used by a processor 1 are is detected and held by a rise detecting circuit 14 and a timing determining circuit 13. In a timing in which a pair of the basic clock and the (n)-fold clock selected newly based on this get into the same logical phase relation, the pair of the clocks selected newly are outputted from a clock output circuit. Consequently, at the time of switching the clocks, a matching is kept between the pair of the clocks made non-selected and the pair of the clocks selected newly.</p> |
