| 摘要 |
A high resolution digital phase-lock loop circuit is described, which is implemented with an input clock reference frequency which is approximately the same as the output frequency of the phase-lock loop. The output is derived from delaying the input clock a variable number of gate delays ranging from no delay to one period of the input clock. A shift register controls the number of gate delays and a 360 degree phase detector initializes the shift register when the output is delayed by one period of the input clock to provide no delay. Gate delay variations due to integrated circuit process, voltage and temperature are compensated for to provide a relatively constant clock phase correction.
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