| 摘要 |
PURPOSE:To shorten the cycle time by connecting plural pairs of divided bit lines, to which plural memory cells are connected, to pairs of main bit lines through selecting gates and providing latch type memory cells between main bit lines and input/output lines. CONSTITUTION:When a row address strobe signal the inverse of RAS is switched from '1' to '0' and the active period begins, contents of a dynamic RAM cell Mij1 and a dummy cell Dij2 connected to a selected word line MWj1 and a dummy word line DWj2 are transferred from divided bit lines DBij and the inverse of DBij to main bit lines BLi and the inverse of BLi, and a latch type memory cell LCi and divided bit lines DBij and the inverse of DBij are disconnected from main bit lines BLi and the inverse of BLi, and divided bit lines DBij and the inverse of DBij are precharged even in the active period of the inverse of RAS, thus shortening the cycle time. |
