| 摘要 |
<p>PURPOSE:To reduce the buffer memory capacity by using a distribution section so as to apply parallel conversion to each of serial input and storing it in a register corresponding to the output via a buffer memory. CONSTITUTION:Serial inputs 21-2n are subject to parallel conversion in the unit of several bytes by S/P converters 31-3n. Then packet resisters 511-51n 5n1-5nm having FiFo function corresponding to the output store the result via packet buffers 41-4n having a common FiFo function. Then a packet is sent to output parallel buses 61-6n so as not to cause any corrosion in a proper order from a packet register corresponding to the same output. Thus, the capacity of the buffer or register by output is enough to be small and the switching system with less memory capacity is obtained.</p> |
