| 摘要 |
A cache memory circuit is responsive to a read request to fetch a data block in a block transfer from a main memory to a cache memory. A sequence of data units into which the data block is divided is successively assigned to a plurality of cache write registers. The assigned data units are simultaneously moved to one of sub-blocks of the cache memory during each of write-in durations with an idle interval left between two adjacent ones of the write-in durations. Each state of the sub-blocks is monitored in a controller. During the idle interval, a following read request can be processed with reference to the states of the sub-blocks even when it requests the data block being transferred. In addition, a read address for the following read request may be preserved in a saving address register to process another read request.
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