发明名称 PHASE LOCKED LOOP
摘要 PURPOSE:To lower the voltage level of the AC component of error signals and make the time constant of a loop filter smaller so as to reduce occurrence of jitters, by providing a means which multiplicatively increases the AC component of phase-compared error signals like frequencies. CONSTITUTION:When a reference signal e1(t) is inputted to a phase dividing circuit 2 from an input terminal 1, phase dividing output signals e1(t)-e4(t) are respectively supplied to phase comparators 3-6 from the circuit 2. When the output signal of a voltage-controlled oscillator(VCO) 10 is inputted to a phase dividing circuit 7, on the other hand, phase dividing output signals e5(t)-e8(t) are respectively supplied to the phase comparators 3-6 from the circuit 7. Therefore, at the phase comparator 3 phase comparison is performed by multiplying the signal e1(t) by the signal e5(t) and a phase comparing output signal e9(t) is outputted. Similarly, phase comparing output signals e10(t)-e12(t) are respectively outputted from the phase comparators 4-6. These signals are supplied to an adder circuit 8 where they are added to each other. The output signal e13(t) of the circuit 8 is supplied to the VCO 10 as an error signal through a loop filter 9.
申请公布号 JPH01133420(A) 申请公布日期 1989.05.25
申请号 JP19870291517 申请日期 1987.11.18
申请人 VICTOR CO OF JAPAN LTD 发明人 ISHIGAKI YUKINOBU
分类号 H03L7/085;H03L7/08;H03L7/087 主分类号 H03L7/085
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