| 摘要 |
PURPOSE:To obtain an interface card capable of constructing a highly reliable system by informing a state to a CPU card by an error latching means and an error state signal transferring means when an error is generated at the time of memory access. CONSTITUTION:The CPU card 21 is connected to the interface card 30 with an error detecting function through an A bus 22 based upon the specification of a microcontroller bus having no interruption signal line and a memory card 24 is also connected to the interface card 30 through a B bus 23 based upon another bus specification. When an error is detected in data sent from the card 24 at the time of memory access based upon the card 21, access operation can be efficiently executed while surely checking the error by the error latching means 31 for latching the address obtained at the time of error generation and the error state signal transferring means 32 for asynchronously transferring an error latch state signal to the card 21 on the CPU side. |
