| 摘要 |
PURPOSE:To heighten the reliability of a processing for a bus error due to a prescribed bus master module other than a central processing unit by designating the bus error due to the bus master module as an exceptional processing factor proper to the central processing unit. CONSTITUTION:When an exceptional processing request for the bus error of a direct memory access control DMAC2 is issued to a CPU1 by asserting a bus error processing request signal BETREQ, the CPU1 accepts the exceptional processing request directly, and after preserving a state, shifts an operation to the execution of a service program immediately without performing the setting and the change of an interruption mask bit. Therefore, the CPU1 starts the execution of the service program for the bus error of the DMAC2 even while it executes another exceptional processing or interruption processing. In such a way, it is possible to shorten a time from the issuing of a bus error exceptional request to the start of the execution of the service program compared with a case to respond by the interruption processing, and to improve the reliability of a system operation. |
