| 摘要 |
A synchronous demodulation system with digital signal output contains a summation circuit receiving an input signal to be demodulated and a control signal. The output of the summation circuit is applied to a synchronous demodulator which feeds into a controller. The controller comprises an integrator, which precedes an A/D converter and a processor that acquires the output pulses of the A/D converter. The processor drives a D/A converter supplying the control signal to the summation circuit so that the summation of the input signal and the output of the D/A converter, averaged over time, leads to an (approximately) zero signal in the synchronous demodulator. Due to digital control the circuit is distinguished by a large dynamic range and high accuracy with simultaneous insensitivity.
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