| 摘要 |
The image processing system includes a fast packet switching network (PSNW) to which send an receive stations (SR, RC) are connected. Each image (AA) to be transmitted is subdivided into blocks by a grid (GR) which is displaceable with respect to the image and the groups of image signals corresponding to these blocks are encoded and transmitted to the network together with a signal (DX, DY), indicating the grid position, as a bitstream having a variable bitrate. The grid position is changed for each image transmission and in the receiver station use is made of a phaselocked loop (PLL) to derive a clock signal from reference signals of this bitstream.
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