发明名称 Shared memory access controller
摘要 A communication system comprises an input-output processor IOP (11) coupled to a plurality of network devices (10) and a protocol processor PP (12), both processors being coupled to a common memory (15). Memory access control means (16) resolves competition between the processors for memory access. Normally, if one of the two processors is accessing the memory, the memory control unit (16) allows that access to be completed before allowing the other processor to access the memory. But if data loss in a network device is imminent, the IOP, is granted a higher priority memory access, the memory access controller aborts (interrupts) any memory access by the PP, allowing the IOP to access the memory immediately.
申请公布号 AU1044899(A) 申请公布日期 1999.06.07
申请号 AU19990010448 申请日期 1998.11.11
申请人 VIRATA LIMITED 发明人 WILLIAM ROBERT STOYE
分类号 G06F13/18 主分类号 G06F13/18
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