| 摘要 |
An EEPROM fabrication process using N-well CMOS technology with a two polysilicon floating gate stack and a double layer of conductive lines providing a small reliable memory cell and high density. Channel stops and field oxide are formed by implanting boron ions, followed by a high-temperature drive-in and oxidation cycle with a 1000 ANGSTROM to 2500 ANGSTROM thick nitride mask covering device areas. The floating gate stack with tunneling window is formed by implanting a first species of N-type impurity, forming a first gate oxide layer, defining a window in the oxide layer over the implant, implanting a second species of N-type impurity through the window, regrowing a thin oxide layer 70 ANGSTROM to 90 ANGSTROM thick in a window, depositing a first polysilicon layer having a thickness of between 2500 ANGSTROM and 3400 ANGSTROM , selectively removing the polysilicon and gate oxide layers to form a floating gate, growing a uniformly thick second oxide layer at 1,000 DEG to 1,050 DEG C. over both the substrate and floating gate, depositing a second polysilicon gate layer and selectively etching away the second polysilicon gate layer to form control gates. Metal coverage in the double layer of conductive lines is improved by rounding corners of glass by means of glass flow and re-flow, corners of intermetal layers by planarization and wet/dry etcing of the via holes, and corners of the first metal by means of wet/dry etching.
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