发明名称 VITERBI DECODER CIRCUIT
摘要 PURPOSE:To simplify the circuit constitution by using an error bit represented by a low-order bit of an output of an A/D converter as an address input of a ROM and outputting only branch metric so as to decrease the input/output bit of the ROM. CONSTITUTION:A branch metric calculation circuit 2 consists of a symbol selection circuit 21 and a ROM 22, a symbol is discriminated by a soft discrimination output of the A/D converter 1 and calculates a branch metric to the symbol. Then a hard discrimination output represented by a high-order digit of the soft discrimination output of the converter 1 and the most significant digit of an error bit represented by a low-order digit are given to the circuit 31 and an error bit is given to an address input of the ROM 22 to output the branch metric. That is, as the address input of the ROM 22, an error bit represented by the low-order bit being the output of the converter 1 is used and only the branch metric is outputted and a common storage content is utilized to all symbols. Thus, the input/output bit of the ROM 22 is decreased to simplify the circuit constitution.
申请公布号 JPH01129617(A) 申请公布日期 1989.05.22
申请号 JP19870288936 申请日期 1987.11.16
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 AIKAWA SATOSHI;SAITO YOICHI
分类号 H04L27/00;H03M13/23;H04L27/38 主分类号 H04L27/00
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