| 摘要 |
PURPOSE: To easily utilize a high-speed pipeline by reading pixel data from a frame butter means and storing the pixel data in an OFF display memory means corresponding to a frame buffer address decided by a vector. CONSTITUTION: When a present stage is not prepared to receive data, a first in first out(FIFO) functions as the FIFO of a depth 1 in the input of respective pipe stages for storing the data sent from an upstream stage. A register clocked by pipeline clocks is added to the respective stages, and before present hold signals sent from a downstream stage are sent to the upstream stage, the signals are latched. Since a processing for latching the data and transferring the hold signals are continued in the pipeline, during a next clock cycle period, by the hold signals of a certain stage, the next upstream stage generates the different hold signals. Thus, constitution is easily extended without being limited by the number of pipe stages. |
