| 摘要 |
PURPOSE:To implement the large area of an active matrix type planar display panel and to implement high definition, by providing a minute crystal silicon film, a polycrystalline silicon film or amorphous silicon film, whose impurity concentration is lower than that of a source electrode or a drain electrode, between a polycrystalline silicon film and at least the drain electrode. CONSTITUTION:Regions 105 having low impurity concentration are provided between a silicon film 102 and a source electrode 106 and a drain electrode 107 immediately beneath a gate. In this structure, when an off state is provided, i.e., when a negative gate voltage is applied in an N-channel transistor and a positive gate voltage is applied in a P-type transistor, an electric field formed by the applied gate voltage and drain voltage is dispersed in the low impurity concentration regions 105. Therefore, the intensity in the electric field at the drain junction part is weakened. Carriers, which move through a trap in the crystal grain boundary in the vicinity of the drain junction are decreased. Therefore, leaking current, which depends on the gate voltage and the drain voltage can be suppressed. |
