| 摘要 |
<p>PURPOSE:To regenerate a correct timing clock for a frame consisting of a start flag, an end flag, and a data part including a special code 'A' by preventing a counter which generates a regeneration clock from being initialized at the position of a leading edge of a reference clock. CONSTITUTION:The start flag waveform 26 of the received signal of a timing extracting circuit 2 is the waveform of a signal including the code 'A', and the output of a NAND gate 10 has a received signal leading edge pulse waveform 63. A signal shown by an initialization inhibition gate waveform 65 is inputted as a signal which generates no initialization signal at the rising of the reference clock to one input terminal of a two-input OR gate 61 to generate an initizalization signal only at the rising of a reference pulse. The initialization inhibition gate signal is generated by inputting the 10-frequency- division output signal of the counter 12 to the D terminal of a D type flip-flop 62 and the 8-frequeney-division output signal of the counter 12, i.e. double clock to the clock terminal of the D type flip-flop 62. The donble clock and regeneration timing clock outputted by the timing extracting circuit are sent to a decoding circuit 3.</p> |
