发明名称 |
SYSTEM FOR PROCESSING MACHINE CHECK INTERRUPTION |
摘要 |
Upon cocurrence of a fault the machine check interruption signal is output, which is detected and stored temporarily in a holding circuit. The interruption signal passes to a code register and to a selector. If the error indicated by the code register and decoder shows that continued operation of the hardware would not be reliable then a converter controls the selector to output an all-zeroes signal from a data store instead of the signal from the holding circuit. The all-zeroes signal acts on a machine check processing routine of a control routine to cause the processor to stop processing of the machine check interruption. |
申请公布号 |
KR890001796(B1) |
申请公布日期 |
1989.05.22 |
申请号 |
KR19830005757 |
申请日期 |
1983.12.05 |
申请人 |
FUJITSU LTD. |
发明人 |
TOSHIO, MATSUMOTO;MOTOKAZU, KATO |
分类号 |
G06F11/00;G06F11/07 |
主分类号 |
G06F11/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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