| 摘要 |
<p>A register interference field (41c) is provided in each instruction constituting an execution code (48), and a processor (40) refers to this field during the interpreting of the instruction and judges in the interior of a processor (40) whether a register interference is occurring or not. When a register interference is occurring, a non-operation (NOP) instruction is inserted between two adjacent instructions for execution. This enables the occurrence of register interference to be prevented without adding a meaningless non-operation (NOP) instruction to the inside of the execution code (48).</p> |
