发明名称 MICROPROCESSOR
摘要 PURPOSE:To execute a branching under a condition to an address of a different upper rank program counter (PC), by constituting the upper rank PC of the address of the first and the second registers, and connecting an output of the second register to an address bus through a buffer. CONSTITUTION:In case when a conditional branch is executed to a different upper rank address, an upper rank address branch instruction is executed, and an address data of an operand part is set to the first register 3. Subsequently, a lower rank address conditional instruction is executed, and when the condition is satisfied, an address of a branch destination is set to a lower rank program counter 5 and the second register 4. In this case, if the condition is not satisfied, it is necessary that the branch destination address data which is set to the first register 3 returns to the address data before executing the branch instruction, and the address data of the second register 5 holds the address data before executing the upper rank address branch instruction, therefore, a data bus buffer 6 is operated, a data of the second register 5 is sent out to an address bus 1, is set to the first register 3, and the processing is completed.
申请公布号 JPS592149(A) 申请公布日期 1984.01.07
申请号 JP19820110834 申请日期 1982.06.29
申请人 CITIZEN TOKEI KK 发明人 HASHIMOTO YUKIO;FUJISAWA KENZOU
分类号 G06F9/32;(IPC1-7):06F9/32 主分类号 G06F9/32
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