| 摘要 |
PURPOSE:To increase a read speed, by providing a clamping means which holds the data of an output buffer at a high level for a specific time after an address change regardless of the potential of the sense data of a sense amplifier. CONSTITUTION:A clock pulse generating circuit PG is added to a static type semiconductor memory. When a change of one of address signals A0-Al-1 and A'0-A'l-1 is detected, a pulse with specific time width is generated through an OR gate OR. When the potential of a clock pulse signal CP is high, the output Dout of the output buffer OB is held high level regardless of the potentials of sense data SD and -SD and then the potential of a data output is varied according to the potential of the sense data SD. Thus, the reading operation speed is increased. |
