Easily cascadable and testable cache memory

摘要

The disclosure relates to a cache memory formed on a single chip wherein the ability to test the address comparator, cache memory diagnostics are improved, cache memory are capable of being read out. The architecture comprises a parity generator, a parity checker, a comparator and an SRAM memory cell array. The cache memory is cascadable for access to an increased address range and to provide increased memory capacity.