发明名称 Asynchronous implementation of a multi-dimensional, low latency, first-in, first-out (fifo) buffer
摘要 A novel FIFO data structure in the form of a multi-dimensional FIFO. For a rectangular multi-dimensional FIFO, data items are received at an input of an N-row-by-M-column FIFO array of cells and transferred to an output, via a predetermined protocol of cell transfers, in the same order as received. Transfer rules or protocol are controlled by a control circuit implemented using asynchronous pipeline modules or a control circuit relying upon transition signaling.
申请公布号 AU9472901(A) 申请公布日期 2002.04.08
申请号 AU20010094729 申请日期 2001.09.25
申请人 SUN MICROSYSTEMS, INC. 发明人 JOSEPHUS EBERGEN
分类号 G06F5/08 主分类号 G06F5/08
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