| 摘要 |
The arrangement consists of a first memory register (SR1), with a first shift device (SE1) connected to it, and a second memory register (SR2), with a second shift device connected to it. A code word is written, left justified, into a first register part (RT1). This code word is arranged right justified in the first shift register (SE1), and the lowest-value bits are fed back to a second register part (RT2) of the first memory register (RE1). In the second memory register (RE2), the arranged data is temporarily stored, to be positioned in the second shift register (SE2) so that data words (DW) of equal width are output at the parallel outputs. The whole arrangement requires only one word cycle. <IMAGE>
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