| 摘要 |
Digital data apparatus comprising a processing unit which can have access to different numbers of memory units over a common data bus. The processing unit can address selectively the memory units with address codes over an address bus. An address code is valid when there is a corresponding memory unit and invalid when no memory unit is provided in respect of it. The validity of an address code is determined in the processing unit by comparing it with a corresponding identification code read from a memory unit addressed by the code. In order to prevent line capacitance on the data bus simulating identification codes to produce an incorrect comparison, one line of the data bus is given the inverse data bit to that of an expected identification code to overcome any spurious bit due to line capacitance. If the identification code is present, the correct data bit in it prevails over the inverse data bit, resulting in a correct validity comparison. If there is no identification code, because there is no memory unit corresponding to the address code concerned, the inverse data bit remains, resulting in correct invalidity comparison. |
