| 摘要 |
According to a manufacturing method of a GaAs FET of this invention, a gate structure (20) is first formed on a GaAs-substrate (10). The gate structure (20) consists of a conductive gate layer (16 min ) and an insulative layer (18 min ), which are in lateral contact with each other on the substrate (10). Each layer (16 min or 18 min ) is isotropically deposited by a CVD process and later anisotropically etched using a RIE process, whereby it has a specific width of the submicron order reduced to an extent substantially equal to an initially deposited thickness thereof. The high frequency property of the GaAs FET can be improved due to the decrease in width of the gate layer (16 min ). Ion implantation is performed with the gate structure used as a mask to provide in the substrate (10) source and drain regions (22, 24) which are self-aligned with the gate structure (20). The drain regions (24) are removed from the gate layer (16 min ) at a distance equal to the width of the insulative layer (18 min ). |
