发明名称 |
REDUNDANCY SCHEME FOR AN MOS MEMORY |
摘要 |
An MOS memory has a main array of memory cells (10, 12) and a plurality of spare memory cells (22, 24). Typically, each memory cell is tested for operability by a conventional probe test. A redundancy scheme is provided for substituting spare memory cells for memory cells found to be defective. An on-chip address controller (38-50) responds to the probe test finding a defective cell by permanently storing and rendering continuously available a fully asynchronous electrical indication of the address of the defective cell. The address controller (38-50) compares its stored data with memory cell information received during normal memory operation, and generates a control signal indicative of the receipt of an address which corresponds to a defective cell. A spare cell selector (106, 108) responds to the control signal by electrically accessing a spare memory cell and by prohibiting access of the defective memory cell. |
申请公布号 |
DE3177025(D1) |
申请公布日期 |
1989.05.11 |
申请号 |
DE19813177025 |
申请日期 |
1981.06.25 |
申请人 |
INMOS CORPORATION |
发明人 |
HARDEE, KIM CARVER;SUD, RAHUL;HEIGHTLEY, JOHN D. |
分类号 |
G06F12/16;G06F11/16;G11C29/00;G11C29/04;(IPC1-7):G06F11/20 |
主分类号 |
G06F12/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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