| 摘要 |
<p>PURPOSE:To perform a fast operation without generating idleness by latching an address and data, supplying them to an EEPROM for a prescribed time, and supplying an address enable signal and a data enable signal from a delay circuit. CONSTITUTION:The address is inputted from a CPU 101 to an AD latch 104, and next, a signal 113 goes an L, and the output signal 115 of an FF109 goes to an H. Thereby, the address is latched at the latch 104, and furthermore, it is inputted to the EEPROM 102 via a bus 105. Also, the data is inputted to a data latch 107 via a data bus 106. Next, a signal 114 goes to the L, and the output signal 116 of an FF10 goes to the H, and the data is latched at a latch 107, and furthermore, it is inputted to the EEPROM 102 via a bus 108. Also, the output signal 118 of the delay circuit 112 goes to the L synchronizing with the signal 116, then, a write operation is started. Next, the signal 116 goes to the H, and after the lapse of a prescribed time, the output signal 117 of an inverter 111 goes to the H, then, a data write operation is completed.</p> |
