发明名称 (A) ;INTERLOCK SEALING DEVICE
摘要 PURPOSE:To inhibit the break-down phenomenon of a gate eldctrode by constitut ing a barrier layer consisting of a mixed crystal semiconductor between a main current path and the gate electrode by a plurality of laminated ultra-thin films, in which mixed crystal compositions repeatedly change. CONSTITUTION:A source electrode 1, a gate electrode 2 and a drain electrode 3 are formed to a laminate consisting of a GaAs layer 5 and an AlxGa1-xAs layer 4, thus constituting a high electron-mobility transistor. With the transistor, electron density on the interface between the layer 4 and the layer 5 is controlled by the voltage of the gate electrode 2, and it is worked as an FET. The layer 4 functions as a barrier layer, but the layer 4 is constituted by laminating a large number of ultra-thin film layers 4-1-4-5, Al concentration therein repeatedly alters. Accordingly, a break-down phenomenon generated when voltage applied to the gate electrode 2 is increased can be inhibited.
申请公布号 JPH0123956(B2) 申请公布日期 1989.05.09
申请号 JP19840247596 申请日期 1984.11.22
申请人 SHINGIJUTSU KAIHATSU JIGYODAN 发明人 SAKAKI HIROYUKI
分类号 H01L29/812;H01L21/20;H01L21/338;H01L29/15;H01L29/205;H01L29/778 主分类号 H01L29/812
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