发明名称 INTERRUPTION CONTROLLER
摘要 <p>PURPOSE:To prevent the error of the operation of executing an interruption request and an interruption response by sending an interruption request signals from adapters to priority order deciding means such as a processor and sending an interruption response signal from a prescribed terminal to the next input terminal in the adapter in accordance with the priority order of the sent interruption request signal. CONSTITUTION:The title device is provided with plural pairs with input terminal to input the interruption request signal or the interruption response signal and the output terminal to output it as one pair and provided with plural adapters 54 connecting the input terminal with the output terminal respectively neighboring each other inside, an internal bus 53 connecting respectively with the input terminals and the output terminals in the same pair relationship, a priority order discriminating means 52 to which the adapters 54 are respectively connected by using the internal bus 53 to determine the priority order to the interruption request signals sent out respectively and a response signal output means 52 to send the interruption response signals respectively back to the adapters 54 in accordance with the determined priority order. Thus, the interruption request terminals of the adapters used for the same purpose are unified and the danger of erring in the operation is eliminated.</p>
申请公布号 JPH01116734(A) 申请公布日期 1989.05.09
申请号 JP19870273158 申请日期 1987.10.30
申请人 NEC CORP 发明人 TSUCHIYA MASAKI
分类号 G06F9/48;G06F1/18;G06F9/02;G06F9/46;G06F13/24 主分类号 G06F9/48
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