| 摘要 |
PURPOSE:To provide a semiconductor memory having rapid input/output with low power consumption, by providing an N-tyre doped region having higher concentration than that of the other N-type regions, in an N-type epitaxial layer serving as a collector of a transistor such that the N-type doped region is in contact with all or a part of the region directly under a Ptype load resistance region. CONSTITUTION:A memory cell comprises an N-type buried layer 2 buried in the surface of a P-type silicon substrate 1 and an N-type epitaxial layer 3 deposited thereon. An NPN transistor is formed thereon, the transistor consisting of a collector region defined by the N-type epitaxial layer 3, a P-type base region 4 and first and second emitter layers 5, 6. A P-type diffused resistance region 7 is formed adjacent to the P-type base region 4 by utilizing a part of the base region 4. An N-type highly doped region 8 is formed directly under the P-type diffused resistance region 7 such that it is in contact with both the region 7 and the N-type buried layer 2. The N-type highly doped region 8 is adjacent to the N-type epitaxial layer 3 providing the collector, region of the NPN transistor. |
