发明名称 I/O CELL OF VERY LARGE SCALE INTEGRATED CIRCUIT
摘要 <p>PURPOSE: To improve the testability of a very large scale integrated circuit by providing an output and input buffer means which respectively supplies an input from an on-chip circuit to a chip pin, and an input from the chip pin to the on-chip circuit. CONSTITUTION: A unit I/O cell introduces an input through a core logic input CLI outputted from a circuit 10 to the core logic of a chip, and receives an output from the core logic at the input point of a core logic output CLO. Functions F16 and F16B, signals F22 and F23B, and output enable line OEN are all cooperatively energized for enabling the CLO, and a signal F18 is energized for enabling an input from a pin P for allowing it to reach the CLI. A circuit 20 can be considered as the bits of an input register which stores information.</p>
申请公布号 JPH01117053(A) 申请公布日期 1989.05.09
申请号 JP19880178306 申请日期 1988.07.19
申请人 CONTROL DATA CORP <CDC> 发明人 JIYUDEI RIN TESUKE;DANIERU JIEEMUSU BATSUKUSUTAA;DON ADORIAN DAANE;BURAIAN DEERU BOOCHIYAAZU;DEBITSUDO HAWAADO AREN;MAIKURU FURANSHISU MAASU
分类号 G01R31/28;G01R31/3185;G06F1/04;H01L21/66;H01L21/82;H01L21/822;H01L27/04 主分类号 G01R31/28
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